This article documents the problems I came across while doing Standard Delay Format (SDF) simulations (not generating SDF files).

Introduction

Standard Delay Format (SDF) files are generated for Dynamic Timing Simulation. Timing info such as device delays, wire delays, and setup/hold time constrains are back-annotated.

SDF files contains:

  • INTERCONNECT wire delay
  • IOPATH device delay
    • rise time: t_PLH (propagate low to high)
    • fall time: t_PHL (propagate high to low)
  • SETUPHOLD timing check
    • posedge
    • negedge
  • IOPATH may vary for different conditions.

Timing value format:

  • (0.000::0.002)
  • (0.000:0.001:0.002)
  • (Min:Typ:Max)

Problems

Inverted signal

Description: When doing some testbanch simulation, we might find that a certain signal (usually an output signal of a module) is inverted. This might cause falures for some test cases (usually submodule tests).

Cause: The original design is not able to drive a large fan-out (to several other modules). The downstream modules could insert invertors to safely drive themselves. The output signal that we are interested in is thus inverted as well.

Solution: As long as the top level tests pass, this problem can be ignored because it does not affect the functionality of our design. To solve such failures, we can manually invert the target signal in testbenches. We can use `ifdef SDF macro so this invertion only takes effect for SDF simulations.

References