Verilog `@(posedge clk)`
This article explains and compares several @(posedge clk)
statements.
Compare
always @(posedge clk) begin
// codes block 1
end
always begin
@(posedge clk);
// codes block 2
end
@(posedge clk) begin
// codes block 3
end
@(posedge clk);
// codes block 4
The first snippet: Execute code block whenever at (posedge clk)
.
The second snippet: Only used in procedural block (in testbench). It behaves the same as the first snippet.
The third snippet: Only used in procedural block (in testbench). Block the following code block until (posedge clk)
. When the posedge arrives, execute code block.
The fourth snippet: It behaves the same as the third snippet.